1. Field of the Invention
The present invention relates to a multilevel interconnection board used for testing semiconductor devices and so forth, and a method of fabricating the same.
2. Description of the Related Art
Tester board (multilevel interconnection board) is used typically in electrical tests of wafers having semiconductor devices formed thereon, in order to make contact between probes and terminals of each semiconductor device. A high level of dimensional accuracy is required for the multilevel interconnection board, because the probes and terminals are disposed at extremely narrow intervals. With recent increase in size of wafers, an extremely high dimensional accuracy has been required for the multilevel interconnection board applied in particular to 300-mm-diameter wafers. In some cases, the multilevel interconnection board is used also under high temperatures. The core base and/or top layer of the multilevel interconnection board are therefore configured using a material having a small thermal expansion coefficient, which is less likely to deform even under high temperatures. Examples of multilevel interconnection board ever put into practical use include those having core base composed of Invar (Fe—Ni-base alloy), Covar (Fe—Ni—Co-base alloy) and carbon-fiber-reinforced plastics (CFRP).
A known structure adopted to the multilevel interconnection board is such as having the thermal expansion coefficient α which decreases in the direction from the core base to the surficial portion. An exemplary structure ever adopted is such as having a carbon-fiber-impregnated resin component (α=1) held between glass-fiber-impregnated resin components (α=15), and the stack is further held between thin-film multilevel resin components (α=20). Adoption of this structure makes it possible to reduce difference between thermal expansion coefficients at the interface between the different materials.
The multilevel interconnection board may, however, be suffered from warping or cracking even if the above-described structure is adopted, due to internal stress concentrated at the interface at a temperature as high as around 150° C. The board may also cause short-circuiting due to impregnation of copper plating solution in the process of forming interconnections in through-holes. This consequently makes the board unavailable for reliability test under high-temperature, high-humidity conditions.
Related arts are disclosed in a patent document 1 (Japanese Patent Application Laid-Open No. 2003-273482), a patent document 2 (Japanese Patent Application Laid-Open No. 3-104191), and a patent document 3 (Japanese Patent Application Laid-Open No. 5-286776).